1. Field of Invention
The present invention generally relates to a circuit to simulate the characteristic of the memory. In particular, the present invention pertains to a circuit to simulate the characteristic of the ferroelectric memory (FeRAM), and more particularly, to a circuit to simulate the polarization relaxation phenomenon of the ferroelectric memory.
2. Description of Related Art
The memory cell of the ferroelectric memory has the same structures as the memory cell of the general dynamical random access memory (DRAM). That is, both of the memory cells comprise a MOS transistor and a capacitor, and use the word line and the bit line to control the operation of the memory cell. The difference between the memory cell of the ferroelectric memory and DRAM is one of the electrodes of the capacitor in FeRAM memory cell needs to be coupled to a drive line, but the drive line does not exist in the memory cell of DRAM. By applying appropriate bias to the word line, the bit line and the drive line of the FeRAM memory cell, the operations of the read and write can be implemented in the FeRAM memory cell.
FIG. 1 shows the hysteresis loop diagram of the ferroelectric memory. The polarization magnitude starts to increase when a voltage is applied to the ferroelectric material. After the applied voltage approaches a constant magnitude (e.g. about 5 V), the polarization magnitude starts to descend. However, when the applied voltage goes down to 0 V, the polarization magnitude goes down to Pr+rather than 0. In practice, the polarization magnitude goes down to Pre1+ rather than Pr+ when the applied voltage going down to 0 V where Pre1+ is a little smaller than Pr+. Thus, there exists a difference value of Pre1+xe2x88x92Pr+. The polarization magnitude starts to increase when the voltage (negative voltage) is continuously applied and approaches a constant magnitude (e.g. about xe2x88x925 V). However, when the applied voltage goes up to 0 V, the polarization magnitude goes up to Prxe2x88x92 rather than 0. In practice, the polarization magnitude goes up to Pre1xe2x88x92 rather than Prxe2x88x92 when the applied voltage goes up to 0 V where Pre1xe2x88x92 is a little smaller than Prxe2x88x92. Thus, there exists a difference value of Prxe2x88x92xe2x88x92pre1xe2x88x92. This results from the polarization relaxation phenomenon.
The polarization relaxation phenomenon results in the non-continuous characteristic of the hysteresis loop while the applied voltage is 0 V. Thus, there exists a gap (Pre1+xe2x88x92Pr+ or Prxe2x88x92xe2x88x92Pre1xe2x88x92) However, the current simulation circuits of the ferroelectric memory are all built based on the ideal hysteresis loop, which does not consider the polarization relaxation phenomenon.
FIG. 2 is a circuit diagram of the conventional ferroelectric memory simulation circuit. The circuit comprises a MOS transistor 10 and a ferroelectric capacitor 12; the structure of this circuit is the same as that of a conventional DRAM except for the ferroelectric capacitor 12 and the plate line PL. The gate of the MOS transistor 10 is coupled to a word line WL, the source of the MOS transistor 10 is coupled to a bit line BL, and the drain of the MOS transistor 10 is coupled to a first electrode of the ferroelectric capacitor 12. The second electrode of the ferroelectric capacitor 12 is coupled to a plate line PL. When the circuit is operating, the operation of writing a xe2x80x9c0xe2x80x9d into the memory cell is accomplished by connecting the plate line PL to ground and applying power VDD to the bit line BL. Contrariwise, the operation of writing a xe2x80x9c1xe2x80x9d into the memory cell is accomplished by connecting the bit line BL to ground and applying power VDD to the plate line PL. Therefore, the write operation of the ferroelectric memory can be implemented. The operation of reading from the ferroelectric memory is accomplished by floating the bit line BL and applying power VDD to the plate line PL.
When considering the original characteristic of the hysteresis loop of the ferroelectric material, the conventional simulation circuit of the ferroelectric memory cannot describe the hysteresis loop correctly. FIG. 3 is a comparison diagram of the hysteresis loop, which compares the hysteresis loop of the actual measurement of the ferroelectric memory and the hysteresis loop using the conventional simulation circuit to simulate the hysteresis loop of the ferroelectric memory. In FIG. 3, the vertical ordinate is the polarization magnitude (xcexcC/cm2), and the horizontal ordinate is the voltage (V). When the polarization magnitude of the ferroelectric material is measured while the applied voltage is 0 V, the polarization magnitude increases and decreases abruptly. That means a gap exists, leading to a non-continuous phenomenon. From the circle portion that marked as 20 in the diagram, the hysteresis loop I that is simulated from the conventional simulation circuit is a continuous variance. That is, the conventional simulation circuit only presents the ideal characteristic of the hysteresis loop, but cannot accurately express the true characteristic of the ferroelectric material.
When the circuit model mentioned above is deployed in the simulation of the ferroelectric memory, it causes an exaggerative phenomenon in the sense voltage such that the sense voltage characteristic of the ferroelectric memory cannot be reflected accurately. One of the most important effects of the ferroelectric memory is the fast-decaying that results from the polarization relaxation phenomenon. The fast-decaying deteriorates the sense margin between the switching level and non-switching level.
As mentioned above, the lack of the capability to simulate the polarization relaxation phenomenon from the conventional simulation circuit affects severely the design and research of the ferroelectric memory. Consequently, the physical characteristics of the ferroelectric memory cannot be simulated efficiently.
Therefore, the objective of the present invention is to provide a circuit to simulate the polarization relaxation phenomenon of the ferroelectric memory. The circuit simulates the non-continuous characteristic of the hysteresis loop of the ferroelectric material and expresses the polarization relaxation phenomenon accurately.
It is therefore another objective of the present invention is to provide a circuit to simulate the polarization relaxation phenomenon of the ferroelectric memory. The circuit simulates the non-continuous characteristic of the hysteresis loop of the ferroelectric material. The circuit simulates the physical characteristics of the ferroelectric memory accurately while conducting the design and research of the ferroelectric memory.
To achieve the above and other objectives, the present invention provides a circuit to simulate the polarization relaxation phenomenon of the ferroelectric memory. The circuit comprises a MOS transistor, a ferroelectric capacitor, a capacitor, and a relaxation voltage source. The gate of the MOS transistor is coupled to the word line and the source of the MOS transistor is coupled to the bit line. A first electrode of the ferroelectric capacitor is coupled to the drain of the MOS transistor and the second electrode of the ferroelectric capacitor is coupled to a plate line. A first electrode of the capacitor is coupled to the drain of the MOS transistor. The first terminal of the relaxation voltage source is coupled to the second electrode of the capacitor, and the second terminal of the relaxation voltage source is coupled to a ground. The capacitance of the capacitor mentioned above is selectively far smaller than the capacitance of the bit line. The output voltage of the relaxation voltage source is logarithmic time dependence.
The present invention further provides a circuit to simulate the polarization relaxation phenomenon of the ferroelectric memory. The circuit comprises a MOS transistor, a ferroelectric capacitor, a capacitor, and a relaxation voltage source. A first electrode of the ferroelectric capacitor is coupled to the drain of the MOS transistor and the second electrode of the ferroelectric capacitor receives the control voltage to supply power to the ferroelectric capacitor. A first electrode of the capacitor is coupled to the drain of the MOS transistor. The relaxation voltage source is coupled to the capacitor. The output voltage of the relaxation voltage source is a logarithmic time dependence.
The present invention thus provides a relaxation voltage source being coupled to the simulation circuit of the ferroelectric memory cell, wherein the output voltage of the relaxation voltage source is a logarithmic time dependence. The circuit can simulate the non-continuous characteristic of the hysteresis loop of the ferroelectric material precisely. Further, the circuit according to the present invention also expresses the physical characteristics of the ferroelectric memory more precisely while conducting the predict and design of the ferroelectric memory.